1. Field of the Invention
The present invention relates to a scanning circuit used in imaging devices and image display devices, and more particularly, to a scanning circuit suitable for high-speed operation.
2. Description of the Related Art
The schematic circuit diagram of FIG. 10 shows the internal structure of a conventional scanning circuit used in imaging devices and image display devices. The scanning circuit shown in FIG. 10 has a number, n, of transfer stages (ta1 to tan) that generate a sequence of pulses. The transfer stages each comprise two switches and two inverters. That is, the k-th (k is a natural number where 1≦k≦n) transfer stage tak comprises: a switch ska one end of which is supplied with an output from the transfer stage ta(k−1); an inverter ika the input side of which is connected to the other end of the switch ska; a switch skb one end of which is connected to the output side of the inverter ika; and an inverter ikb the input side of which is connected to the other end of the switch skb (FIG. 10 shows the first to the third stages). The output from the inverter ikb is the output outk of the transfer stage tak. For example, when the scanning circuit of FIG. 10 is used with a solid-state image sensing device in an imaging apparatus, the output outk is output as a signal for scanning the solid-state image sensing device.
To the scanning circuit of FIG. 10, clock signals Xa and Xb for alternately operating the switches provided in each transfer stage are supplied with phases that are shifted relative to one another. In the k-th transfer stage tak, when the clock signal Xa is high, the switch ska is on, and when the clock signal Xb is high, the switch skb is on.
Therefore, in a case where the output out(k−1) of the transfer stage ta(k−1) is output as a high-level pulse signal, when the clock pulse Xa is supplied to turn on the switch ska, a high-level signal is input to the inverter ika via the switch ska and a low-level signal is output from the inverter ika. Then, when the switch ska is turned off and the clock pulse Xb is supplied to turn on the switch skb, a low-level signal is input to the inverter ikb via the switch skb and a high-level signal is output from the inverter ikb as an output outk of the transfer stage tak. At this time, the output out(k−1) of the transfer stage ta(k−1) becomes low.
Then, when the clock pulse Xa is again supplied to turn on the switch ska, the low-level signal is input to the inverter ika via the switch ska and a high-level signal is output from the inverter ika. Then, when the clock pulse Xb is supplied to turn on the switch skb, the high-level signal is input to the inverter ikb via the switch skb and a low-level signal is output from the inverter ikb as the output outk of the transfer stage tak.
Assume now that a start pulse that is high is supplied to the switch s1a of the transfer stage ta1 while the clock signal Xb is low, and the clock pulse Xa is supplied while the start pulse is high, as shown in FIG. 11. At this time, the switches s1a to sna are turned on by the clock pulse Xa. Moreover, the output of the inverter i1a becomes low and the outputs of the inverters i2a to ina become high.
Then, when the start pulse is driven low and the clock pulse Xb is supplied, the switches s1b to snb are turned on. At this time, the output of the inverter i1b becomes high and the outputs of the inverters i2b to inb become low. Consequently, as shown in FIG. 11, the output out1 of the transfer stage ta1 becomes high and the outputs out2 to outn of the transfer stages ta2 to tan become low.
Then, when the clock pulse Xa is supplied again, the switches s1a to sna are turned on, the output of the inverter i2a becomes low and the outputs of the inverters i1a and i3a to ina become high. Then, when the clock pulse Xb is supplied, the switches s1b to snb are turned on, the output of the inverter i2b becomes high and the outputs of the inverters i1b and i3b to inb become low. Consequently, as shown in FIG. 11, the output out2 of the transfer stage ta2 becomes high and the outputs out1 and out3 to outn of the transfer stages ta1 and ta3 to tan become low.
Thus, by alternately supplying the high-level clock pulses Xa and Xb, as shown in FIG. 11, the outputs out1 to outn of the number, n, of transfer stages ta1 to tan are output in order of out1, out2, out3, . . . as high-level pulse signals for scanning. The width (pulse width) of the output waveform of the output outk is the same as the length of one period of the clock signals Xa and Xb.
In the conventional scanning circuit that outputs a signal for scanning in this manner, since the clock pulses Xa and Xb are alternately supplied so as not to overlap each other, it is necessary that the pulse width of one clock be less than half the pulse width of the output outk. On the other hand, there is an upper limit to the frequency of the externally input clock signals Xa and Xb. Therefore, the pulse width of the output outk from the scanning circuit can be reduced only to a width corresponding to the limit of the frequency of the clock signals Xa and Xb. Consequently, the driving speed of the driving circuit of an imaging device or an image display device having such a scanning circuit is limited by the scanning circuit, so that a sufficient driving speed cannot be achieved.